Towards a Systematic Design of Fault-Tolerant Asynchronous Circuits

Accommodating billions of transistors on a single die, VLSI technology has reached a scale where principal physical limitations have a strong impact on design principles. Among the particular challenges are maintaining the synchronous clock abstraction in settings where wiring delays dominate over switching delays, and coping with increasing transient failure rates. In an attempt to address some of these challenges, we recently developed a clocking scheme called DARTS1. The cornerstone of this approach is a distributed fault-tolerant Tick Generation (TG) unit that implements an adaptation of a faulttolerant clock synchronization algorithm originally developed in the distributed computing context [1]. Each functional unit on the chip is augmented with a dedicated TG unit here that generates its clock signal. Since all these TG units communicate with each other (by exchanging their clock signals), all non-faulty TG units actually supply mutually synchronized clock signals to their attached functional units [2]. The implementation of the TG units [3] required a design process that was quite different from the traditional one: First, the TG circuitry dedicated to generating the chip’s clock signals naturally mandated an implementation in asynchronous logic. Second, our fault-tolerance requirements made it necessary to cope with lost/faulty clock signal transitions, which rendered a delay-insensitive approach impossible. And last but not least, we had to bridge the gap between the highlevel distributed algorithm’s view with its mathematical proofs, and the low-level VLSI implementation with its tool-based verification techniques. This paper (resp. its extended version [4]) lays down the cornerstones of a design process suitable for fault-tolerant asynchronous (FASY) circuits.